The present invention is related to the subject matter of the following U.S. Patent application No. 09/210,133: Chen et al., Transaction Merging with Multiple Set Buffer Pool Bus Bridge, Ser. No. 09/210,127; Chen et al., Interrupt Response in a Multiple Set Buffer Pool Bus Bridge, and Ser. No. 09/210,134 Chen et al., Read Request Performance of a Multiple Set Buffer Pool Bus Bridge, all filed on the filing date of this application.
1. Field of the Present Invention
The present invention generally relates to the field of microprocessor based computers and more particularly to organizing and managing buffers in a bus bridge to improve the performance of a computing system.
2. History of Related Art
Microprocessor based computer systems typically employ a variety of adapters or peripheral devices to provide extended capabilities to the system and to decrease the processing load required of the central processor or processors. As computing systems continue to increase in performance and complexity, the number of peripheral devices has increased commensurately often necessitating the use of multiple layers of peripheral busses to accommodate all of the required peripheral devices and to provide expansion capacity to the system user. Typically, specialized circuits or devices generally referred to as bus bridges provide the functionality required to enable the various busses within a system to communicate information. The increased importance of peripheral devices in modem computers, from the simplest consumer oriented machines to high end enterprise systems, has generated increased attention to the performance of peripheral busses and bus bridges. Increasing the number of instructions a central processor can execute per second results in only a marginal increase in system performance if the system""s bus bridges and peripheral busses are operating at their performance limits. Typically, however, the ability to improve bus bridge performance is constrained by compatibility concerns. Accommodating the large base of peripheral devices designed according to a preexisting bus specification limits the ability to make changes to any bus bridge design. Accordingly, improvements to a particular bus bridge design should, to the greatest extent possible, be compatible with existing bus protocols.
Because bus bridges may be coupled between busses operating at different clock frequencies or between a bus that is currently accessible and a bus that is busy, bridges routinely implement a pool of storage buffers for temporarily storing transactions in transit from one bus to another. Each storage buffer is typically configured to store any of a variety of transactions. Some bus bridges, such as bridges compliant with the PCI specification, include the capability to merge or combine transactions. Such capabilities, however, are all too commonly underutilized because the buffer pool organization of conventionally designed bridges coupled with constraints imposed by the bus specifications prevent or significantly diminish the opportunities to take advantage of the combining or merging capabilities of the bridge. Moreover, conventional bridge designs and buffer pool organizations in which transactions are stored in a common pool can unnecessarily hamper performance of commonly invoked procedures such as interrupt handling routines by failing to associate buffered transactions with their sources. Without information concerning the origin of buffered transactions, many common procedures are forced, under the constraints of the relevant bus specification, to account for each transaction in the buffer pool, regardless of whether a given transaction is relevant to the procedure. Accordingly, it is highly desirable to implement a bus bridge designed to take greater advantage of opportunities to combine buffered transactions and improve the efficiency of commonly invoked procedures such as interrupt handling while maintaining compatibility with existing bus specifications and protocols.
The problems identified above are in large part addressed by a system and bus bridge design in which the bridges buffer pool is organized into multiple buffer sets and configured to associate each buffer set with a corresponding peripheral device. With this organization, the source of buffered transactions can be maintained without requiring tag bits or other information that is not in compliance with existing bus specifications. The source information can be utilized beneficially to improve the performance and reduce overhead associated with a variety of tasks and routines.
Broadly speaking, a first application of the present invention contemplates a bus bridge including a buffer pool and steering logic. The buffer pool is organized as a plurality of buffer sets including at least a first and second buffer set. The steering logic is adapted to store transactions originating from a first peripheral device to the first buffer set and transactions originating from a second peripheral device to the second buffer set thereby preserving origin information associated with each buffered transaction. In one embodiment, the transactions arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge is suitably adapted for combining two or more transactions within each buffer set to produce a single transaction. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus that is coupled to the bus bridge through bus interface logic. The primary bus may comprise a host bus connected to one or more processors. Alternatively, the primary bus may comprise an additional PCI bus or other peripheral bus.
The first application of the present invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. The bridge includes a pool of buffer sets including a first buffer set and a second buffer set. The bridge includes steering logic configured to store transactions into buffer sets associated with the peripheral device corresponding to the transaction such that first device transactions are stored in the first buffer set, second device transactions stored in the second buffer set, and so forth. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals. The bridge is preferably configured to produce at least first and second grant signals for the first and second peripheral devices respectively to indicate mastership of the secondary bus. In this embodiment, the steering logic is suitably configured to receive the first and second grant signals and to determine therefrom the source of a subsequent transaction.
The first application of the present invention still further contemplates a method of buffering transactions in a bus bridge according to the source of the transaction. A first transaction is received and a first peripheral device identified as its source. In response to identifying the first peripheral device as the source of the first transaction, a first buffer set is selected and the first transaction stored in the first buffer set such that the source of the first transaction is indicated by the presence of the first transaction within the first buffer set. Similarly, a second transaction from a second peripheral device is received and its source identified. A second buffer set is then selected and the second transaction stored in the second buffer set. In an embodiment emphasizing the combining of transactions, additional transactions are received and stored in the appropriate buffer sets. Combining of transactions within a buffer set may then proceed without affecting the contents of the remaining buffer sets. In this manner, a third transaction received from the first peripheral device could be stored in the first buffer set and combined, if appropriate, with the first transaction without regard to transactions in other buffer sets, such as the second transaction, in the second buffer set. Combining occurs when multiple sequential memory write transactions are combined into a single bus transaction. I/O performance is improved with multiple buffer sets organized based on bus grant level by making transactions flowing through one buffer set essentially unaffected by transactions flowing through another buffer set. Thus, additional write combining and merging is facilitated.
A second application of the present invention contemplates a bus bridge coupled between primary and secondary busses. The bridge includes a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to receiving a read request transaction from the first peripheral device while allowing transactions in the second buffer set to be unaffected. In this manner the execution time of read requests is independent of the contents of the buffer sets not associated with the peripheral device that issued the read request. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate the source of a subsequent transaction to be received via the secondary bus. The transactions pushed ahead of and in response to the read request transaction may be previous posted memory write transactions while the bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to the first and second buffer sets respectively. Transactions flowing through the first buffer set would need to follow conventional PCI ordering rules as would transactions flowing through the second buffer set. However, with this invention, transactions in the first buffer set and the second buffer set are allowed to be unordered relative to each other. This results in improved performance since a read transactions from the first device only has to push or pull posted memory write data in the first buffer set, allowing other buffer sets to be unaffected. Additionally, performance is improved since transactions flowing through one buffer set can be essentially unaffected and unordered relative to transactions flowing through another buffer set.
The second application of the present invention further contemplates a computer system that includes processor, a bus bridge coupled to the processor via a primary bus, a system memory coupled to the primary bus, and first and second peripheral devices coupled to the bus bridge via a secondary bus. The bus bridge includes steering logic and a buffer pool comprised of first and second buffer sets. The steering logic is configured to store transactions received from the first and second peripheral devices in the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions stored in the first buffer set onto the primary bus ahead of a read request transaction from the first peripheral device without affecting the transactions stored in the second buffer set. The bridge is preferably configured to arbitrate mastership of the secondary bus among the peripheral devices in response to first and second request signals received by the bridge from the first and second peripheral devices respectively. The bridge is further configured to produce first and second grant signals to the first and second peripheral devices respectively, to indicate the result of the arbitration of the secondary bus. The steering logic is configured to receive the grant signals and determine the source of a subsequent transaction on the secondary bus. The transactions received from the first and second peripheral devices include posted write transactions which are required by the bus specification to be executed in order. Other transactions received from the first and second peripheral device can also include delayed read requests, delayed read completions, delayed write requests, and delayed write completions. Detailed definitions of all of these transaction types are included in the PCI specifications.
The second application of the present invention still further contemplates a method of executing read requests through a bus bridge. A first posted memory write transaction is received from a first peripheral device and its source identified. Upon identifying the first transaction""s source, a first buffer set is selected and the first transaction posted therein. A second posted memory write transaction from a second peripheral device is then received, its source identified, a second buffer set selected, and the second transaction stored in the second buffer set. The first posted memory write transaction is then pushed from the first buffer set in response to receiving a read request transaction from the first peripheral device while the second posted memory write transaction in the second buffer set is unaffected. In one embodiment, determining the source of the first and second transactions is achieved by receiving first and second request signals from the first and second peripheral devices respectively and arbitrating mastership of a secondary bus in response to the first and second request signals. In embodiments in which the secondary bus over which the transactions are received is a PCI bus, the first and second transactions include posted memory write transactions. Usually, the pushing of the first posted memory write transaction includes pushing the first transaction out of the bridge towards system memory via the primary bus.
A third application of the present invention contemplates a bus bridge including a buffer pool comprised of a first buffer set and a second buffer set. The first buffer set is associated with a first peripheral device and the second buffer set associated with a second peripheral device. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor.
The third application of the present invention further contemplates a system including a processor coupled to a host bus, a system memory, a bus bridge coupled between the host bus and a secondary bus, and first and second peripheral devices coupled to the secondary bus. The bus bridge includes a buffer pool comprised of a first buffer set and a second buffer set. The first buffer set is associated with the first peripheral device and the second buffer set is associated with the second peripheral device. The bridge is configured to receive interrupts. Upon receiving an interrupt, the bridge is further configured to identify the interrupt source, select a buffer set associated with the interrupt source, and flush transactions in the selected buffer set, all prior to forwarding the interrupt to the processor. In one embodiment, the bridge, the first and second peripheral devices, and the secondary bus are compliant with the PCI specification. The bridge is configured in one embodiment such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. The bridge is configured in one embodiment to receive unique first and second interrupt signals from the first and second peripheral devices respectively. The flushing of the selected buffer set preferably comprises pushing transactions stored in the selected buffer set into system memory via the host bus.
The third application of the present invention still further contemplates a method of handling interrupts. A first peripheral device is identified as an interrupt source in response to receiving an interrupt. Prior to forwarding the interrupt to a processor, write request transactions stored in a selected buffer set are flushed in response to the identification of the interrupt source wherein the selected buffer set is associated with the interrupt source. After the flushing of the transactions, the interrupt is forwarded to a processor. In this manner, receipt of the interrupt by the processor informs the processor that the selected buffer set has been flushed. In one embodiment, the identifying of the interrupt source includes receiving a first interrupt signal generated by and unique to the first peripheral device. The flushing of transactions posted in the appropriate buffer set comprises pushing the transactions into system memory via a primary bus. The pushing of the transactions stored in the first buffer set is preferably achieved while retaining transactions stored in a second buffer set. A new bit in the adapter that is set during configuration indicates to the device""s device driver that the bridge will flush the buffer following the interrupt, prior to forwarding the interrupt to the system. When this bit is set, the device driver will know it does not have to execute a read to the device to flush data following an interrupt. Performance is improved by avoiding the necessity of either a read to memory executed by the device or a read to the device following an interrupt executed by the device driver to push or pull data to memory. These operations would be time consuming compared to simply flushing the write data following the interrupt as described in this invention.
A fourth application of the present invention contemplates a bus bridge with a pool of buffer sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to flush the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals control the target of the read request issued by the processor. In one embodiment, the flushing of the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected, Preferably, transactions flushed by the bus bridge comprise posted memory write cycles.
The fourth application of the present invention still further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge coupled between the host bus and a secondary bus. The bus bridge includes a pool of buffer sets including at least first and second buffer sets and first and second peripheral devices coupled to the secondary bus. The bus bridge is configured to identify the first peripheral device as a target of a load request issued by the processor and, in response to the identification, to flush or pull data in the first buffer set ahead of the load completion data, where the first buffer set is associated with the first peripheral device. The first and second buffer sets each include at least one buffer for temporarily storing transactions bound for the system memory via the host bus. In one embodiment, the secondary bus and the bus bridge are compliant with the PCI specification (i.e., a PCI-PCI bridge or a PCI-host bridge). The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the processor is configured to issue the read request in response to receiving an interrupt. The source of the interrupt is preferably the target of the load request.
The fourth application of the present invention still further contemplates a method of flushing or pulling data buffered in a bus bridge. A first peripheral device is identified as the peripheral device targeted by a load request issued by a processor. A first buffer set, which is associated with the first peripheral device, is then selected from a pool of buffer sets in response to identifying the first peripheral device. Write transactions stored in the first buffer set are then flushed or pulled ahead of the load return data in response to the load request while leaving transactions stored in a second buffer set unaffected. Preferably, the identification of the first peripheral device includes receiving first and second device select signals from the first peripheral device and a second peripheral device respectively. These first and second device select signals are asserted by their respective peripheral devices wherein the device select signals are indicative of the target of the load request. In one common embodiment, the processor issues the load request in response to detecting an interrupt to insure that data buffered in the bridge is pulled back to system memory. The source of the interrupt is preferably the target of the load request. The flushing or pulling of the write transactions in the first buffer set includes, in one embodiment, pulling the transactions into a system memory coupled to the processor via a primary bus. The transactions suitably pulled during the flushing or pulling of data of the first buffer include posted memory write transactions.